------------------------------------------------//库声明
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

------------------------------------------------//实体定义
entity division is
port 
(    fpshu  : in integer range 130 to 781250;
     clk_in : in std_logic;
    clk_out : out std_logic
		   );
end entity division;

------------------------------------------------//结构体定义
architecture behave of division is

------------------------------------------------//元件1定义 
component div_even is
generic(data_width : integer := 20 );
port
(    fpshu  : in std_logic_vector(data_width - 1 downto 0);
     clk_in : in std_logic;
    clk_out : out std_logic
	     );
end component div_even;
 
------------------------------------------------//元件2定义 
component div_odd is
generic(data_width : integer := 20);
port
(    fpshu  : in std_logic_vector(data_width - 1 downto 0);
     clk_in : in std_logic;
    clk_out : out std_logic
	     );
end component div_odd; 
 
------------------------------------------------//信号量定义 
signal clk_temp_1,clk_temp_2 : std_logic;
signal fpshu_temp :  std_logic_vector(19 downto 0);

begin

------------------------------------------------//端口映射
u1: div_even port map(fpshu_temp,clk_in,clk_temp_1);
u2: div_odd  port map(fpshu_temp,clk_in,clk_temp_2);

fpshu_temp <= conv_std_logic_vector(fpshu,20);

------------------------------------------------//进程1，选通输出
    process(clk_in,fpshu_temp)
    begin
        if fpshu_temp(0)= '0' then
            clk_out <= clk_temp_1;
        else clk_out <= clk_temp_2;
        end if;
    end process;
 
end architecture behave;